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1 ir3838mpbf rev 1.41 fig. 1. typical application diagram description the ir3838 supirbuck tm is an easy-to-use, fully integrated and highly efficient dc/dc regulator. the onboard pwm controller and mosfets make ir3838 a space-efficient solution, providing accurate power delivery for low output voltage applications. ir3838 is a versatile regulator which offers programmability of switching frequency and current limit while operates in wide input and output voltage range. the switching frequency is programmable from 250khz to 1.5mhz for an optimum solution. it also features important protection functions, such as pre-bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. ir3838 offers margini ng capability through vref pin. during the margining operation, pgood tracks vref via feedback to ensure correct status of the output voltage. the internal ldo enables the device to operate from a single supply. this internal ldo can be bypassed when an external bias voltage is available. features ? greater than 96% maximum efficiency ? single 16v application ? single 5v application ? wide output voltage range: 0.6v to 0.9*vin ? continuous 10a load capability ? programmable switching frequency up to 1.5mhz ? internal digital soft-start ? enable input with voltage monitoring capability ? hiccup mode over current protection ? internal ldo ? external synchronization ? enhanced prebias start up ? external reference for margining purposes ? input for tracking applications ? integrated mosfet drivers and bootstrap diode ? operating junction temp: -40 o c 2 ir3838mpbf rev 1.41 package information 5mm x 6mm power qfn (top view) 13 pvin 12 sw 11 pgnd 17 gnd 1 23 4 5 6 7 8 9 16 15 fb vref comp gnd rt ocset pgood sync vin vp boot absolute maximum ratings (voltages referenced to gnd unless otherwise specified) ? pvin, vin ?????????????????? -0.3v to 25v ? vcc/ldo_out ??????.??..??..???.?? -0.3v to 8v (note2) ? boot ??????????????..???.?.. -0.3v to 33v ? sw ?????????????? ??..??? -0.3v to 25v (dc), -4v to 25v (ac, 100ns) ? boot to sw ??..??????????? ?..?. -0.3v to vcc+0.3v (note1) ? ocset ????????????????..?? -0.3v to 30v ? input / output pins ????????????... ... -0.3v to vcc+0.3v (note1) ? pgnd to gnd ?????...???????.??.?. -0.3v to +0.3v ? storage temperature range .......... .......................... -55c to 150c ? junction temperature range .... ............................ ... -40c to 150c (note2) ? esd classification ??????????? ??? jedec(2kv) ? moisture sensitivity level??????...?????. jedec level 2 @260 c ( note 5 ) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the devi ce at these or any other conditions beyond those indicated in the operational s ections of the specifica tions are not implied. note1: must not exceed 8v note2: vcc must not exceed 7.5v for junction temperature between -10 o c and -40 o c enable vcc/ldo_out 10 14 w / c 2 w / c 35 o pcb j o ja = = - 4000 17 ir3838mtrpbf m 750 parts per reel 17 pin count ir3838mtr1pbf package description m package designator ordering information
3 ir3838mpbf rev 1.41 block diagram fig. 2. simplified block diagram of the ir3838
4 ir3838mpbf rev 1.41 pin description pin name description 1 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier 2 vref external reference voltage, can be used for margining operation. a 100nf capacitor should be connected between this pin and gnd. 3 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb to provide loop compensation 4 gnd signal ground for internal reference and control circuitry 5 rt use an external resistor from this pin to gnd to set the switching frequency 6 ocset current limit set point. a resistor from this pin to sw pin will set the current limit threshold 7 pgood power good status pin. output is open drain. connect a pull up resistor from this pin to vcc 8 sync external synchronization, this pin is used to synchronize the device?s switching with an external clock. it is recommended that the external sync clock be set to 20% above the free-running frequency. if not used, this pin can be left floating. 9 vin input voltage for internal ldo. a 1.0f capacitor should be connected between this pin and pgnd. if external supply is connected to vcc/ldo_out pin, this pin should be left floating. 10 v cc /ldo_out input bias voltage, output of internal ldo. place a minimum 2.2f cap from this pin to pgnd 11 pgnd power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 12 sw switch node. this pin is connected to the output inductor 13 pvin input voltage for power stage 14 boot supply voltage for high side driver, a 100nf capacitor should be connected between this pin and sw pin. 15 enable enable pin to turn on and off the device, if this pin is connected to pvin pin through a resistor divider, input voltage uvlo can be implemented. 16 vp input to error amplifier for tracking purposes 17 gnd signal ground for internal reference and control circuitry
5 ir3838mpbf rev 1.41 recommended operating conditions symbol definition min max units pvin input voltage for power stage 1.5 16 vin input voltage for internal ldo * 7.0 16 vcc/ldo_out supply voltage * 4.5 6.5 boot to sw supply voltage 4.5 7.5 v o output voltage 0.6 0.9*vin v i o output current 0 10 a fs switching frequency 225 1650 khz t j junction temperature -40 125 o c * vcc/ldo_out can be connected to an external regulated supply ( 5v). if so, the vin input should be left unconnected. parameter symbol test condition min typ max unit power stage power losses p loss v in =12v, v o =1.8v, i o =10a, fs=600khz, l=0.6uh, note4 2 w top switch r ds(on)_top v boot -v sw =5.0v, i d =10a,tj=25c 17.1 26 bottom switch r ds(on)_bot v cc =5.0v, i d =10a 8.5 11 m ? bootstrap diode forward voltage i(boot)= 30ma 180 260 470 mv sw=0v, enable=0v 6 sw leakage current isw sw=0v, enable=high, vp=0v 14 a supply current v in supply current (standby) i in(standby) enable low , no switching, 400 a v in supply current (dyn) i in(dyn) enable high, fs=500khz, vin=12v 12 ma internal regulator (ldo) output voltage intvcc vin(min)=7.0v, io=0-50ma, cload=2.2uf 4.7 5.2 5.7 v intvcc dropout intvcc_drop io=50ma, cload=2.2uf 50 150 mv short circuit current ishort 70 ma internal digital soft start soft start clock frequency clk(ss) note4 168 200 254 khz soft start ramp rate ramp(ss) 0.2 mv/us electrical specifications unless otherwise specified, these specification apply over, 7.0v 6 ir3838mpbf rev 1.41 electrical specifications (continued) unless otherwise specified, these specification apply over, 7.0v2.0v -1 +1 input offset voltage vos_vref vfb-vref, vref=0.6v, vp>2.0v -1 1 % input bias current ifb(e/a) -1 +1 ? a input bias current ivp(e/a) -1 +1 ? a sink current isink(e/a) 0.40 0.85 1.2 ma source current isource(e/a) 8 10 13 ma slew rate sr note4 7 12 20 v/ ? s gain-bandwidth product gbwp note4 20 30 40 mhz dc gain gain note4 100 110 120 db maximum voltage vmax(e/a) 3.4 3.5 3.75 v minimum voltage vmin(e/a) 150 220 mv common mode voltage 0 1.2 v oscillator rt voltage 0.665 0.7 0.735 v rt=59k 225 250 275 rt=28.7k 450 500 550 frequency range f s rt=9.53k, note4 1350 1500 1650 khz ramp amplitude vramp note4 1.8 vp-p ramp offset ramp(os) note4 0.6 v min pulse width dmin(ctrl) note4 70 ns max duty cycle dmax fs=250khz 91 % fixed off time note4 300 ns sync frequency range 20% above free running frequency 225 1650 khz sync pulse duration 100 200 ns sync high 2 sync level threshold sync low 0.6 v reference voltage feedback voltage vfb vref pin floating, vp=vcc 0.6 v 0 o c 7 ir3838mpbf rev 1.41 electrical specifications (continued) parameter symbol test condition min typ max unit fault protection fs=250khz 10.4 11.8 13.2 fs=500khz 21.5 24.4 27.3 ocset current i ocset fs=1500khz 68 77 86 a oc comp offset voltage v offset note4 -6 0 +6 mv ss off time ss_hiccup 4096 cycles thermal shutdown note4 140 thermal hysteresis note4 20 c under voltage lockout v cc -start-threshold v cc _uvlo_start vcc rising trip level 4.06 4.26 4.46 v cc -stop-threshold v cc _uvlo_stop vcc falling trip level 3.76 3.96 4.16 v enable-start-threshold enable_uvlo_start supply ramping up 1.14 1.2 1.36 enable-stop-threshold enable_uvlo_stop supply ramping down 0.75 0.85 0.95 v enable leakage current ien enable=3.3v 10 a pgood fb rising, vref < 1.2v 115 %vref power good upper threshold vpg(upper) fb rising, vref > 1.5v 115 %vp upper threshold delay vpg(upper)_dly fb falling 256/fs s fb rising, vref < 1.2v 85 %vref power good lower threshold vpg(lower) fb rising, vref > 1.5v 85 %vp lower threshold delay vpg(lower)_dly fb rising 256/fs s soft start delay time tdelay(delay) note4 10 ms pgood voltage low pg(voltage) i pgood =-5ma 0.5 v tracker comparator upper threshold vpg(tracker_upper) vp rising, vref > 1.5v 0.5 tracker comparator lower threshold vpg(tracker_lower) vp falling, vref > 1.5v 0.3 v tracker comparator delay tdelay(tracker) vp rising, vref > 1.5v 256/fs s note3 : cold temperature performance is guaranteed via correlation using statistical quality control. not tested in production. note4 : guaranteed by design but not tested in production note5 : upgrade to industrial/msl2 level applies from date codes 1141 (marking explained on application note an1132 page 2). products with prior date code of 1141 are qualified with msl3 for consumer market.
8 ir3838mpbf rev 1.41 typical efficiency and power loss curves vin=12v, vcc=5v (external), io=1a-10a, f s =600khz, room temperature, no air flow the table below shows the inductors used for each of the output voltages in the efficiency measurement. vo [v] l [h] mfr p/n dcr [m ? ] 1.2 0.51 vitec 59pr9876n 0.29 1.8 0.72 wurth elek. 744 325 072 1.3 3.3 1.2 wurth elek. 744 325 120 1.8 5.0 1.2 delta mpl1055-1r2 2.9 80 82 84 86 88 90 92 94 96 98 12345678910 load current (a) efficiency (%) 1.2v 1.8v 3.3v 5.0v 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 12345678910 load current (a) power loss (w) 1.2v 1.8v 3.3v 5.0v
9 ir3838mpbf rev 1.41 typical efficiency and power loss curves vin=12v, vcc/ldo_out=5.2v, io=1a-10a, fs=600khz, room temperature, no air flow the same inductors as listed on the previous page have been used. 76 78 80 82 84 86 88 90 92 94 96 98 12345678910 load current (a) efficiency (%) 1.2v 1.8v 3.3v 5.0v 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 12345678910 load current (a) power loss (w) 1.2v 1.8v 3.3v 5.0v
10 ir3838mpbf rev 1.41 v cc(uvlo) stop 3.76 3.81 3.86 3.91 3.96 4.01 4.06 4.11 4.16 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [v] iin(dyn) 11.5 11.7 11.9 12.1 12.3 12.5 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [ma] typical operating characteristics (-40 o c - 125 o c), f s =500 khz iin(standby) 160 180 200 220 240 260 280 300 320 340 360 380 400 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [a] frequency 450 460 470 480 490 500 510 520 530 540 550 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [khz] iocset(500khz) 21.5 22.5 23.5 24.5 25.5 26.5 27.5 -40-20 0 20406080100120140 temp [oc] [a] vcc(uvlo) start 4.06 4.11 4.16 4.21 4.26 4.31 4.36 4.41 4.46 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [v] enable(uvlo) start 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 -40-20 0 20406080100120140 temp [oc] [v] enable(uvlo) stop 0.75 0.77 0.79 0.81 0.83 0.85 0.87 0.89 0.91 0.93 0.95 -40-20 0 20406080100120140 temp [oc] [v] vcc_ldo 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [v] vfb 0.588 0.592 0.596 0.600 0.604 0.608 0.612 -40 -20 0 20 40 60 80 100 120 140 temp [oc] [v]
11 ir3838mpbf rev 1.41 rdson of mosfets over temperature at vcc=5v rdson of sync-fet versus vcc at different temperatures 6 8 10 12 14 16 18 20 22 24 -40-20 0 20406080100120140 temperature [c] resistance [m-ohm] sync-fet ctrl-fet 5 6 7 8 9 10 11 12 13 14 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 vcc [v] rds_on_sync [m ? ] -40c 0c 25c 65c 100c 125c
12 ir3838mpbf rev 1.41 enable the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under-voltage lockout (uvlo) circuit. therefore, the ir3838 will turn on only when the voltage at the enable pin exceeds this threshold, typically, 1.2v. if the input to the enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the ir3838 does not turn on until the bus voltage reaches the desired level (fig. 3). only after the bus voltage reaches or exceeds this level will the voltage at enable pin exceed its threshold, thus enabling the ir3838. therefore, in addition to being a logic input pin to enable the ir3838, the enable feature, with its precise threshold, also allows the user to implement an under-voltage lockout for the bus voltage (pvin). this is desirable particularly for high output voltage applications, where we might want the ir3838 to be disabled at least until pvin exceeds the desired output voltage level. figure 4a. shows the recommended start-up sequence for the normal (non-tracking, non- sequencing) operation of ir3838, when enable is used as a logic input. in this operating mode vref is left floating. figure 4b. shows the recommended startup sequence for sequenced operation of ir3838 with enable used as logic input. for this mode of operation, vref is left floating. figure 4c shows the recommended startup sequence for tracking operation of ir3838 with enable used as logic input. for this mode of operation, vref is connected to a voltage greater than 1.5v. circuit description theory of operation introduction the ir3838 uses a pwm voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the switching frequency is programmable from 250khz to 1.5mhz and provides the capability of optimizing the design in terms of size and performance. ir3838 provides precisely regulated output voltage programmed via two external resistors from 0.6v to 0.9*vin. the ir3838 operates with an internal bias supply voltage of 5.2v (ldo) which is connected to the vcc/ldo_out pin. this allows operation with single supply. the ic can also be operated with an external supply from 4.5v to 6.5v, allowing an extended operating input voltage (pvin) range from 1.5v to 16v. for using the internal supply, the vin pin should be connected to pvin pin. if an external supply is used, it should be connected to vcc/ldo_out pin and the vin pin should be left floating. the device utilizes the on-resistance of the low side mosfet (sync fet) as current sense element. this method enhances the converter?s efficiency and reduces cost by eliminating the need for external current sense resistor . ir3838 includes two low r ds(on) mosfets using ir?s hexfet technology. these are specifically designed for high efficiency applications. under-voltage lockout and por the under-voltage lockout circuit monitors the voltage of vcc/ldo pin and the enable input. it assures that the mosfet driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. normal operation resumes once vcc/ldo and enable rise above their thresholds. the por (power on ready) signal is generated when all these signals reach the valid logic level (see system block diagram). when the por is asserted the soft start sequence starts (see soft start section). fig. 3. normal start up, device turns on when the bus voltage reaches 10.2v pvin (12v) vcc (5.2v) enable ss 10. 2 v enable threshold = 1.2v
13 ir3838mpbf rev 1.41 fig. 5b. pre-bias startup pulses fig. 5a. pre-bias startup fig. 4b. recommended startup for sequencing operation (ratiometric or simultaneous) fig. 4c. recommended startup for memory tracking operation (vtt-ddr) vref this pin reflects the internal reference voltage which is used by the error amplifier to set the output voltage. in most operating conditions this pin is only connected to an external bypass capacitor and it is left floating. in tracking mode this pin should be connected to an external voltage greater than 1.5v and less than 7v. for margining applications, an external voltage source is connected to vref pin and overrides the internal reference voltage. the external voltage source should have a low internal resistance (<100 ? ) and be able to source and sink more than 25a. pre-bias startup ir3838 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (control fet) is generated. figure 5a shows a typical pre-bias condition at start up. the sync fet always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. the number of these startup pulses for the sync fet is internally programmed. figure 5b shows a series of 32, 16, 8 startup pulses. fig. 4a. recommended startup for normal operation pvin (12v) vcc (5.2v) enable > 1. 2 v ss vp
14 ir3838mpbf rev 1.41 soft-start the ir3838 has a digital internal soft-start to control the output voltage rise and to limit the current surge at the start-up. to ensure correct start-up, the soft-start sequence initiates when the enable and vcc rise above their uvlo thresholds and generate the power on ready (por) signal. the internal ss signal linearly rises with the rate of 0.2mv / s from 0v to 2v. figure 6 shows the waveforms during soft start (also refer to figure 11). the normal start up time is fixed, and is equal to: during the soft start the ocp is enabled to protect the device for any short circuit and over current condition. fig. 6. theoretical operation waveforms during soft-start (non tracking / non sequencing) ?? (1) - - - - - - - - - - - - - - 3ms s 0.2mv/ 0.7v - 1.3v t start ? ? ? operating frequency the switching frequency can be programmed between 250khz ? 1500khz by connecting an external resistor from r t pin to gnd. table 1 tabulates the oscillator frequency versus r t . shutdown the ir3838 can be shutdown by pulling the enable pin below its 0.85 v threshold. this will tri-state both, the high side driver as well as the low side driver. table 1. switching frequency and i ocset vs. external resistor ( r t ) over-current protection the over current protection is performed by sensing current through the r ds(on) of the sync fet. this method enhances the converter?s efficiency and reduces cost by eliminating a current sense resistor. as shown in figure 7, an external resistor (r ocset ) is connected between ocset pin and the switch node (sw) which sets the current limit set point. an internal current so urce sources current ( iocset ) out of the ocset pin. this current is a function of rt and hence, of the free-running switching frequency. table 1. shows iocset at different switching frequencies. the internal current source develops a voltage across r ocset . when the sync fet is turned on, the inductor current flows through q2 and results in a voltage at ocset which is given by: an over current is detected if the ocset pin goes below ground. however, to avoid false tripping , due to the noise generated when the sync fet is turned on, the ocp comparator is enabled about 200ns after sync-fet is turned on . i ) r r i v l (on ds ocset ocset ocset .(3) .......... ) ( ) ( ? ? ? ? .....(2) .......... .......... .......... ) (k a) ( ? ? t ocset r i 700 71.7 1400 9.76 75.15 1500 9.31 55.1 1100 12.7 60.85 1200 11.5 65.4 1300 10.7 48.95 1000 14.3 44.3 900 15.8 39.3 800 17.8 34.1 700 20.5 29.54 600 23.7 24.35 500 28.7 19.6 400 35.7 300 47.5 i ocset ( a) f s (khz) r t (k ? ) 1400 9.76 1500 9.31 1100 12.7 1200 11.5 1300 10.7 1000 14.3 900 15.8 800 17.8 700 20.5 600 23.7 500 28.7 400 35.7 14.7 300 47.5 i ocset ( a) f s (khz) r t (k ? )
15 ir3838mpbf rev 1.41 as mentioned earlier, an over current is detected if the ocset pin goes below ground. hence, at the current limit threshold, v ocset =0. then, for a current limit setting i limit ,r ocset is calculated as follows: fig. 7. connection of over current sensing resistor an over-current detection trips the ocp comparator, latches ocp signal and cycles the soft start function in hiccup mode. the hiccup is performed by making the internal ss signal equal to zero and counting the number of switching cycles. the soft start pin is held low until 4096 cycles have been completed. the ocp signal resets and the converter recovers. after every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. an optional 10pf-22pf filt er capacitor can be connected from ocset pin to pgnd. it is recommended to use this capacitor for very narrow duty cycle applications (pulse-width <150ns). thermal shutdown temperature sensing is provided inside ir3838. the trip threshold is typically set to 140 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets and resets the internal soft start. automatic restart is initiated when the sensed temperature drops within the operating range. there is a 20 o c hysteresis in the thermal shutdown threshold. i i r r ocset limit on ds ocset (4) .... .......... .......... ) ( * ? external synchronization the ir3838 incorporates an internal circuit which enables synchronization of the internal oscillator (using rising edge) to an external clock. an external resistor from rt pin to gnd is still required to set the free-running frequency close to the sync input frequency. this function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple pol (point of load) regulators are used. applying the external signal to the sync input changes the effective value of the ramp signal (vramp/vosc). equation (5) shows that the effective amplitude of the ramp is reduced after the external sync signal is applied. more difference between the frequency of the sync and the free-running frequency results in more change in the effective amplitude of the ramp signal. therefore, since the ramp amplitude takes part in calculating the loop-gain and bandwidth of the regulator, it is recommended to not use a sync frequency which is much higher than the free-running frequency (or vice versa). in addition, the effective value of the ramp signal, given by equation (5), should be used when the compensator is designed for the regulator. the pulse width of the external clock, which is applied to the sync, should be greater than 100ns and its high level should be greater than 2v, while its lower level is less than 0.6v. for more information refer to the oscillator section in page- 6. if this pin is left floating, the ic will run with the free running frequency set by the resistor rt. output voltage tracking and sequencing the ir3838 can accommodate user programmable tracking and/or sequencing options using vp, vref, enable, and power good pins. in the block diagram presented on page 3, the error-amplifier (e/a) has been depicted with three positive inputs. ideally, the input with the lower voltage is used for regulating the output voltage and the other two inputs are ignored. in practice the voltage of the other two inputs should be about 200mv greater than the low- voltage input so that their effects can completely be ignored. for normal operation, vp is tied to vcc (1.5v < vp < vcc) and vref is left floating (with a bypass capacitor). .... .......... .......... f f . vosc sync run _ free (5) ? ? 8 1 1
16 ir3838mpbf rev 1.41 therefore, in normal operating condition, after enable goes high the ss ramps up the output voltage until vfb (voltage of feedback/fb pin) reaches about 0.6v. then vref takes over and the output voltage is regulated (refer to fig. 11). tracking-mode operation is achieved by connecting vref to vcc (1.5v0.6v the error-amplifier switches to vref and the output voltage is regulated with vref. fig. 8. application circuit for simultaneous and ratiometric sequencing tracking and sequencing operations can be implemented to be simultaneous or ratiometric (refer to figures 9 and 10). figure 8 shows typical circuit configuration for sequencing operation. with this power-up configuration, the voltage at the vp pin of the slave reaches 0.6v before the fb pin of the master. if r e /r f =r c /r d , simultaneous startup is achieved. that is, the output voltage of the slave follows that of the master until the voltage at the vp pin of the slave reaches 0.6 v. after the voltage at the vp pin of the slave exceeds 0.6v, the internal 0.6v reference of the slave dictates its output voltage. in reality the regulation gradually shifts from vp to internal vref. the circuit shown in fig. 8 can also be used for simultaneous or ratiometric tracking operation if vref of the slave is connected to vcc. table 2 on page 17 summarizes the required conditions to achieve simultaneous / ratiometric tracking or sequencing operations. fig. 10 typical waveforms in tracking mode of operation: (a) simultaneous, (b) ratiometric fig. 9 typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric
17 ir3838mpbf rev 1.41 timing diagram of pgood functions fig.11 non-sequence startup and vref margin (vp =vcc) table 2. the required conditions to achieve simultaneous / ratiometric tracking and sequencing operations with the circuit configuration of fig. 8 r e /r f >r c /r d ramp up from 0v > 1.5v ratiometric tracking r e /r f =r c /r d ramp up from 0v > 1.5v simultaneous tracking r a /r b >r e /r f > r c /r d ramp up from 0v 0.6v ratiometric sequencing r a /r b > r e /r f =r c /r d ramp up from 0v 0.6v simultaneous sequencing - > 1.5v 0.6v (float) normal (non-sequencing, non-tracking) required condition vp vref (slave) operating mode r e /r f >r c /r d ramp up from 0v > 1.5v ratiometric tracking r e /r f =r c /r d ramp up from 0v > 1.5v simultaneous tracking r a /r b >r e /r f > r c /r d ramp up from 0v 0.6v ratiometric sequencing r a /r b > r e /r f =r c /r d ramp up from 0v 0.6v simultaneous sequencing - > 1.5v 0.6v (float) normal (non-sequencing, non-tracking) required condition vp vref (slave) operating mode internal ss 0 0 0 0 vref pgood 256/fs fb 0.7v 1.3v 2.0v ssok 256/fs 0.6v 1.15*vref 0.85*vref power good output the ic continually monitors the output voltage via feedback (fb pin). the feedback voltage is compared to a threshold. the threshold is set differently at different operating modes and the results of the comparison sets the pgood signal. figures 11, 12, and 13 show the timing diagram of the pgood signal at different operating modes. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation.
18 ir3838mpbf rev 1.41 fig.13 vp sequence and vref margin fig.12 vp tracking (vref >1.5v, ss=h) timing diagram of pgood functions
19 ir3838mpbf rev 1.41 minimum on time considerations the minimum on time is the shortest amount of time for which the control fet may be reliably turned on, and this depends on the internal timing delays. for the ir3838, the typical minimum on-time is specified as 70 ns. any design or application using the ir3838 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 150 ns. this is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. in any application that uses the ir3838, the following condition must be satisfied: the minimum output voltage is limited by the reference voltage and hence v out(min) = 0.6 v. therefore, for v out(min) = 0.6 v, therefore, at the maximum recommended input voltage 16v and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 250 khz. conversely, for operation at the maximum recommended operating frequency (1.65 mhz) and minimum output voltage (0.6v), the input voltage (pvin) should not exceed 2.42v, otherwise pulse skipping will happen. at low output voltages (below 1v) specially at vo=0.6v, it is recommended to design the compensator so that the bandwidth of the loop does not exceed 1/10 of the switching frequency. v/s 10 4 ns 150 v 0.6 v v 6 in in ? ? ? ? ? ? ? ? s (min) on (min) out s f t v f maximum duty ratio considerations a fixed off-time of 300 ns maximum is specified for the ir3838. this provides an upper limit on the operating duty ratio at any given switching frequency. thus, the higher the switching frequency, the lower is the maximum duty ratio at which the ir3838 can operate. to allow some margin, the maximum operating duty ratio in any application using the ir3838 should still accommodate about 500 ns off-time. fig 14. shows a plot of the maximum duty ratio v/s the switching frequency, with 300 ns off-time. s out s on f v f d t v in ? ? ? (min) on out s in s in out (min) on on (min) on t v f v f v v t t t ? ? ? ? ? ? ? fig. 14. maximum duty cycle v/s switching frequency. 50 55 60 65 70 75 80 85 90 95 250 450 650 850 1050 1250 1450 1650 switching frequency (khz) max duty cycle (%)
20 ir3838mpbf rev 1.41 when an external resistor divider is connected to the output as shown in figure 16. equation (8) can be rewritten as: for the calculated values of r8 and r9 see feedback compensation section. bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected to the source of the control fet . this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c6). the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled down to ground. the capacitor charges towards v cc through the internal bootstrap diode (figure 17), which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c6 is approximately given as when the control fet turns on in the next cycle, the capacitor node connected to sw rises to the bus voltage v in . however, if the value of c6 is appropriately chosen, the voltage v c across c6 remains approximately unchanged and the voltage at the boot pin becomes: application information design example: the following example is a typical application for ir3838. the application circuit is shown on page 26. enabling the ir3838 as explained earlier, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage as shown in figure 15. for a typical enable threshold of v en = 1.2 v for a v in (min) =10.2v, r 1 =49.9k and r 2 =6.8k ohm is a good choice. programming the frequency for f s = 600 khz, select r t = 23.7 k ? , using table 1. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6v. the divider ratio is set to provide 0.6v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: khz 600 = 30 % 2 a 10 = v 8 1 = max) v 2 13 ( v 12 = s o o o o in f transient load % v v i . v . v ) for ! ? ? fig. 16. typical application of the ir3838 for programming the output voltage (9) .... .......... .......... .......... v v v r r ref o ref ? ? ? ? ? ? ? ? ? ? ? 8 9 v v v d cc c (10) ...... .......... .......... ? ? fb ir3624 v out r 9 r 8 ir3838 ir3838 enable v in r 2 r 1 v r r r * v en (min) in (6) .......... 1.2 ? ? ? 2 1 2 v v v r r en ) min in( en (7) .......... ? ? 1 2 .....(8) .......... .......... .......... ? ? ? ? ? ? ? ? ? ? ? 9 8 1 r r v v ref o fig. 15. using enable pin for uvlo implementation (11) .......... .......... .......... .......... d cc in boot v v v v ? ? ?
21 ir3838mpbf rev 1.41 inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. a low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor . the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: where: if i 42.5%( i o ), then the output inductor is calculated to be 0.6 h. select mpl104-0r6 from delta ( l =0.6 h) which provides a compact, low profile inductor suitable for this application. output capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criteria is normally based on the value of the effective series resistance (esr). however the actual capacitance value and the equivalent series inductance (esl) are other contributing components. these components can be described as a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple current generated during the on time of the control fet should be provided by the input capacitor. the rms value of this ripple is expressed by: where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. for i o =10a and d = 0.15, the i rms = 3.6a. ceramic capacitors are recommended due to their peak current capabilit ies. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is advisable to have 3x10uf, 16v ceramic capacitors, ecj-3yx1c106k from panasonic. in addition to these, although not mandatory, a 1x330uf, 25v smd capacitor eev-fk1e331p may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. ....(12) .......... .......... ) d ( d i i o rms ? ? ? ? 1 (13) .. .......... .......... .......... in o v v d ? ) ( i ? cycle duty time on turn frequency switching current ripple inductor voltage output voltage input maximum ? ? ? ? ? ? d t f i v v s o in ?? (14) . .......... .......... .......... s in o o in s o in f * i v v v v l f d t ; t i l v v ? ? ? ? ? ? ? ? ? ? ? ? ? 1 fig. 17. bootstrap circuit to generate vc voltage (15) ..... .......... .......... 8 s o l ) c ( o o in ) esl ( o l ) esr ( o ) c ( o ) esl ( o ) esr ( o o f * c * i v esl * l v v v esr * i v v v v v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
22 ir3838mpbf rev 1.41 where: ? v o = output voltage ripple ? i l = inductor ripple current since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the ir3838 can perform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. therefore it is advisable to select ceramic capacitors due to their low esr and esl and small size. five of taiyo yuden?s jmk212bj476mg-t (47uf, 6.3v, 3m ? ) capacitors is a good choice. it is also recommended to use a 0.1f ceramic capacitor at the output for high frequency filtering. feedback compensation the ir3838 is a voltage mode controller. the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed-loop transfer function with the highest 0 db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, ?40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 18). the resonant frequency of the lc filter is expressed as follows: figure 18 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system runs the risk of being unstable. the ir3838 uses a voltage-type error amplifier with high-gain (110db) and high-bandwidth (30mhz). the output of the amplifier is available for dc gain control and ac phase compensation. the error amplifier can be compensated either in type ii or type iii compensation. local feedback with type ii compensation is shown in fig. 19. this method requires that the output capacitor should have enough esr to satisfy stability requirements. if the output capacitor?s esr generates a zero at 5khz to 50khz, the zero generates acceptable phase margin and the type ii compensator can be used. the esr zero of the output capacitor is expressed as follows: (16) .. .......... .......... .......... o o lc c l f ? ? ? 2 1 fig. 18. gain and phase of lc filter (17) ....... .......... .......... o esr *esr*c f ? ? 2 1 fig. 19. type ii compensation network and its asymptotic gain plot
23 ir3838mpbf rev 1.41 the transfer function ( v e /v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: first select the desired zero-crossover frequency ( f o ): use the following equation to calculate r3: where: v in = maximum input voltage v osc = amplitude of the oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 8 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: use equations (20), (21) and (22) to calculate c4. one more capacitor is sometimes added in parallel with c4 and r3. this introduces one more pole which is mainly used to suppress the switching noise. (18) ..... 1 4 8 4 3 c sr c sr z z ) s ( h v v in f out e ? ? ? ? ? ? ?? (20) ........ .......... .......... (19) ......... .......... .......... ......... 4 3 8 3 2 1 c * r * f r r s h z ? ? ?? (21 ) 1/10 ~ 1/5 f and o ....... s esr o f * f f ? ? (22) ....... .......... .......... 2 8 3 lc in esr o osc f * v r * f * f * v r ? the additional pole is given by: the pole sets to one half of the switching frequency which results in the capacitor c pole : for a general solution for unconditional stability for any type of output capacitors, and a wide range of esr values, we should implement local feedback with a type iii compensation network. the typically used compensation network for voltage-mode controller is shown in figure 20. (23) ....... .......... .......... .......... o o z lc z c * l * . f f % f 2 1 75 0 75 ? ? ...(24) .......... .......... .......... pole pole p c c c * c * r * f ? ? 4 4 3 2 1 (25) .. .......... .......... *f *r c *f *r c s s pole 3 4 3 1 1 1 ? ? ? fig.20. type iii compensation network and its asymptotic gain plot v out v ref r 9 r 8 r 10 c 7 c 3 c 4 r 3 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain (db) |h(s)| db fb comp
24 ir3838mpbf rev 1.41 again, the transfer function is given by: by replacing z in and z f according to figure 20, the transfer function can be expressed as: the compensation network has three poles and two zeros and they are expressed as follows: cross over frequency is expressed as: based on the frequency of the zero generated by the output capacitor and its esr, relative to crossover frequency, the compensation type can be different. table 3 shows the compensation types for relative locations of the crossover frequency. (31) .......... .....(30) .......... .......... .......... .......... (29) ..... .......... ) .......(28 .......... .......... .......... .......... ......(27) .......... .......... .......... .......... .......... .......... 8 7 10 8 7 2 4 3 1 3 3 3 4 3 4 3 3 7 10 2 1 2 1 2 1 2 1 2 1 2 1 2 1 0 r * c * ) r r ( * c * f c * r * f c * r * c c c * c r * f c * r * f f z z p p p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (32) .. .......... .......... .......... o o osc in o c * l * * v v * c * r f 2 1 7 3 ? the higher the crossover frequency is, the potentially faster the load transient response will be. however, the crossover frequency should be low enough to allow attenuation of switching noise. typically, the control loop bandwidth or crossover frequency ( f o ) is selected such that the dc gain should be large enough to provide high dc-regulation accuracy. the phase margin should be greater than 45 o for overall stability. for this design we have: v in =12v v o =1.8v v osc =1.8v v ref =0.6v l o =0.6h c o =5x47f, esr 3m ? each it must be noted here that the value of the capacitance used in the compensator design must be the small signal value. for instance, the small signal capacitance of the 47uf capacitor used in this design is 26uf at 1.8 v dc bias and 600 khz frequency. it is this value that must be used for all computations related to the compensation. the small signal value may be obtained from the manufacturer?s datasheets, design tools or spice models. alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f lc and using equation (16) to compute the small signal c o . these result to: f lc =18 khz f esr =2.04 mhz f s /2 =300 khz ? ? s o f f * 1/10 ~ 1/5 ? compensator type f esr vs f 0 typical output capacitor type ii f lc < f esr < f 0 < f s /2 electrolytic type iii f lc < f 0 < f esr sp-cap, ceramic in f out e z z ) s ( h v v ? ? ? ?? ?? (26) .... ) c sr ( c c c * c sr ) c c ( sr r r sc ) c sr ( ) s ( h 7 10 3 4 3 4 3 3 4 8 10 8 7 4 3 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
25 ir3838mpbf rev 1.41 select crossover frequency f 0 =100 khz since f lc 26 ir3838mpbf rev 1.41 application diagram: fig. 21. application circuit diagram for a 12v to 1.8 v, 10 a point of load converter suggested bill of materials for the application circuit: part reference quantity value description manufacturer part number cin 1 330uf smd elecrolytic, fsize, 25v, 20% panasonic eev-fk1e331p 3 10uf 1206, 16v, x7r, 20% panasonic - ecg ecj-3yx1c106k lo 1 0.6uh 11.5x10x4mm, 20%, 1.5m ? delta mpl104-0r6 co 5 47uf ceramic, 6.3v, 0805, x5r,20% taiyo yuden jmk212bj476mg-t r1 1 49.9k thick film, 0603,1/10 w,1% rohm mcr03ezpfx4992 r2 1 6.8k thick film, 0603,1/10w,1% rohm mcr03ezpfx6801 r t 1 23.7k thick film, 0603,1/10w,1% rohm mcr03ezpfx2372 r ocset 1 6.04k thick film, 0603,1/10 w,1% rohm mcr03ezpfx6041 r pg 1 10k thick film, 0603,1/10w,1% rohm MCR03EZPFX1002 cref 1 0.1uf 0603, 25v, x7r, 10% panasonic - ecg ecj-1vb1e104k r3 1 3.32k thick film, 0603,1/10w,1% rohm mcr03ezpfx3321 c3 1 150pf 50v, 0603, npo, 5% panasonic- ecg ecj-1vc1h151j c4 1 5.6nf 0603, 50v, x7r, 10% panasonic - ecg ecj-1vb1h562k c6 1 0.1uf 0603, 25v, x7r, 10% panasonic - ecg ecj-1vb1e104k r8 1 4.02k thick film, 0603,1/10w,1% rohm mcr03ezpfx4021 r9 1 2.0k thick film, 0603,1/10w,1% rohm mcr03ezpfx2001 r10 1 127 thick film, 0603,1/10w,1% panasonic - ecg erj-3ekf1270v c7 1 2200pf 0603, 50v, x7r, 10% panasonic - ecg ecj-1vb1h222k cvcc 1 2.2uf 0603, 10v, x5r, 10% panasonic - ecg ecj-1vb1a225k u1 1 ir3838 supirbuck, 10a, pqfn 5x6mm international rectifier ir3838mpbf
27 ir3838mpbf rev 1.41 typical operating waveforms vin=12v, vcc/ldo=5.2v, vo=1.8v, io=0-10a, room temperature, no air flow fig. 25: output voltage ripple, 10a load ch 1 : v out fig. 26: inductor node at 10a load ch 3 :sw fig. 27: short (hiccup) recovery ch 1 :v out , ch 2 :pgood , ch 4 :iout fig. 22: start up at 10a load (note 6) ch 1 :v out ch 2 :pgood ch 3 :en ch 4 : v in fig. 24: start up with 1.62v prebias, 0a load, ch 1 :v out ch 2 : pgood ch 3 : en fig. 23: start up at 10a load (note 6) ch 1 :v out ch 2 :pgood ch 3 :vcc ch 4 : v in
28 ir3838mpbf rev 1.41 typical operating waveforms vin=12v, vcc/ldo=5.2v, vo=1.8v, room temperature, no air flow note6: enable (en) is tied to vin via a resistor divider and triggered when vin is exceeding above 10.2v. fig. 28: transient response 1a-4a load (0.5a/us) ch 1 :v out , ch 4 :i o
29 ir3838mpbf rev 1.41 typical operating waveforms vin=12v, vcc/ldo=5.2v, vo=1.8v, io=0-10a, room temperature, no air flow fig.29: bode plot at 10a load shows a band width of 94khz and phase margin of 51 degrees
30 ir3838mpbf rev 1.41 layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make all the connections for the power components in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, output capacitors and the ir3838 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pvin pin of ir3838. the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass components such as capacitors for vin, vcc, vref and vp should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. pgnd vin agnd vout pgnd vin agnd vout the connection between the ocset resistor and the sw pin should not share any trace with the connection between the bootstrap capacitor and the sw pin. instead, it is recommended to use a kelvin connection of the trace from the ocset resistor and the trace from the bootstrap capacitor at the sw pin. also, place the ocset resistor close to the device. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 4-layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. figure 30 illustrates the implementation of the layout guidelines outlined above, on the irdc3838 4 layer demoboard. all bypass caps should be placed as close as possible to their connecting pins. resistors rt and r ocset should be placed as close as possible to their pins. enough copper & minimum length ground path between input and output pgnd vin agnd vout compensation parts should be placed as close as possible to the comp pin . fig. 30a. irdc3838 demoboard layout considerations ? top layer pgnd
31 ir3838mpbf rev 1.41 pgnd fig. 30c. irdc3838 demoboard layout considerations ? mid layer 1 fig. 30d. irdc3838 demoboard layout considerations ? mid layer 2 feedback trace should be kept away form noise sources fig. 30b. irdc3838 demoboard layout considerations ? bottom layer single point connection between agnd & pgnd, should be close to the supirbuck, kept away from noise sources. analog ground plane power ground plane the trace which connects r ocset to sw node is separated from the trace which connect boot cap to sw node boot cap uses separate trace from r ocset to be connected to sw node
32 ir3838mpbf rev 1.41 pcb metal and components placement evaluations have shown that the best overall pe rformance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. for further information, please refer to ?supirbuck? multi-chip module (mcm) power quad flat no-lead (pqfn) board mounting application note.? ( an-1132 ) pcb metal pad sizing (all dimensions in mm) pcb metal pad spacing (all dimensions in mm)
33 ir3838mpbf rev 1.41 solder resist it is recommended that the lead lands are non solder mask defined (nsmd). the solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure nsmd pads. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
34 ir3838mpbf rev 1.41 stencil design stencils for pqfn can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. evaluations have shown that the best overall pe rformance is achieved using the stencil design shown in following figure. this design is for a stencil thickness of 0.127mm (0.005"). the reduction should be adjusted for stencils of other thicknesses. stencil pad sizing (all dimensions in mm) stencil pad spacing (all dimensions in mm)
35 ir3838mpbf rev 1.41 milimiters inches milimiters inches dim min max min max dim min max min max a 0.800 1.000 0.0315 0.0394 l 0.350 0.450 0.0138 0.0177 a1 0.000 0.050 0.0000 0.0020 m 2.441 2.541 0.0961 0.1000 b 0.375 0.475 0.1477 0.1871 n 0.703 0.803 0.0277 0.0316 b1 0.250 0.350 0.0098 0.1379 o 2.079 2.179 0.0819 0.0858 c 0.203 ref. 0.008 ref. p 3.242 3.342 0.1276 0.1316 d 5.000 basic 1.969 basic q 1.265 1.365 0.0498 0.0537 e 6.000 basic 2.362 basic r 2.644 2.744 0.1041 0.1080 e 1.033 basic 0.0407 basic s 1.500 1.600 0.0591 0.0630 e1 0.650 basic 0.0256 basic t1, t2, t3 0.401 basic 0.016 bacis e2 0.852 basic 0.0335 basic t4 1.153 basic 0.045 basic t5 0.727 basic 0.0286 basic ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the industrial market ( note5 ) visit us at www.irf.com fo r sales contact information data and specifications subject to change without notice. 11/11

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